The present invention relates to electronic circuits, and more particularly, to techniques for configuring multi-path feedback loops.
A phase-locked loop (PLL) can be used to generate clock signals. A PLL typically includes a phase detector that compares a reference clock signal to a feedback clock signal to generate one or more phase error signals. A charge pump generates a control voltage based on the phase error signals. A loop filter filters the control voltage. A voltage-controlled oscillator generates one or more output clock signals. The frequency of the output clock signals of the oscillator varies based on changes in the filtered control voltage.
A PLL typically introduces jitter peaking into its output clock signals. Jitter peaking is caused by the closed loop jitter transfer function of the PLL exceeding unity within a range of frequencies. The jitter in the reference clock signal is amplified within this range of frequencies, causing more jitter in the output clock signals than exists in the reference clock signal. Jitter peaking can be a problem in systems that have several PLLs cascaded together in series such that an output clock signal of each PLL (except the last PLL) is used to generate the reference clock signal for the next PLL in the series.